Optimization of the thermal performance of the 3d ics utilizing the integrated chip-size double-layer or multi-layer microchannels

ABSTRACT

A three-dimensional integrated circuit apparatus includes a three-dimensional integrated circuit including a group of integrated double-layer microchannels (DLMC) and multi-layer microchannels (MLMC) with optimized thermal performance for the three-dimensional integrated circuit.

CROSS REFERENCE TO PROVISIONAL APPLICATION

This patent application claims priority under 35 U.S.C. § 119 to U.S.Provisional Patent Application Ser. No. 63/356,873 entitled“Optimization of the Thermal Performance of the 3D ICs Utilizing theIntegrated Chip-size Double-layer or Multi-layer Microchannels,” whichwas filed on Jun. 29, 2022, and is incorporated herein by reference inits entirety.

TECHNICAL FIELD

Embodiments are related to integrated circuits. Embodiments are alsorelated to three-dimensional (3D) integrated circuits. Embodimentsfurther relate to chip-size integrated double-layer microchannels (DLMC)and multi-layer microchannels (MLMC) used in three-dimensionalintegrated circuits.

BACKGROUND

A three-dimensional integrated circuit (3D IC) is a metal-oxidesemiconductor-integrated circuit manufactured by stacking silicon wafersor dies and interconnecting them vertically using through-silicon vias(TSVs), such that they behave as a single integrated device to achievehigher performance, lower power consumption, higher functional density,lower transistor packaging density, and a smaller form factor thanconventional two-dimensional integrated circuits.

Due to drastically increased integration density of 3D ICs, the task ofremoving a large amount of dispersed heat from a constrained space isbeyond the capability of conventional cooling techniques. Theaccumulated heat within the device and the hotspot temperature areundesirable for the electrical performance since many electricalparameters are adversely affected by a substantial temperature rise[1-3]. As such effective heat removal from the 3D structure is extremelycrucial.

Tavakkoli et al. [4,5] performed a comprehensive thermal analysis of 3Dhigh performance chips using numerical simulations. The effect ofparametric changes in the geometrical configuration on the temperaturedistribution and hotspot temperatures were extensively highlighted, suchas size, number and spacing, TSV arrangements (nominal TSVs, uniformTSVs and core-concentrated TSVs). The investigation also sufficientlyoutlined the impact of the thermophysical properties of the chip andcooling fluid on the flow and heat transfer. Their results presented thekey features to be used for establishing optimized design and setup of3D ICs.

Wang et al. [6] performed an analysis to study the effects of geometricand thermal properties of multi-layer nominal 3D IC chips on thetemperature hotspots with different distributions of processors(overlapped cores and staggered cores). They found that the larger thenumber of the chip layers, the higher the hotspot temperature is; buthaving a large Reynolds number can help decrease the hotspottemperature. Tavakoli, Salimpour and Vafai [7] investigated theoptimization of the heat spreader by inserting the boron arsenidestructures, including radial, one level of paring and two-level paringstructures. Their results have shown that the two-level paring boronarsenide structures in the heat spreader achieved the superiorperformance by reducing the hotspot temperature up to 14%.

Tavakoli and Vafai [8] also established a numerical investigation of theoptimal distribution of a limited amount of high thermal conductivitymaterial to enhance the heat removal from 3D ICs. Single-layer anddouble-layer ring shape inserts were studied and optimized for thethermal performance. Their results show that the maximum temperature ofthe 3D IC is reduced up to 10% for the optimal condition and the size ofthe heat sink and heat spreader can be 200% smaller compared to theconventional ones.

Lu and Vafai [9] had established that rectangular-shaped heat pipes(RSHP) and disk-shaped heat pipes (DSHP) heat sinks substantiallyimproved the overall thermal performance and reduced the hotspottemperatures by 7 K and 11 K on average, respectively. Furthermore,utilizing these innovative RSHP or DSHP as the heat spreader underneaththe RSHP or DSHP heat sink further optimizes the thermal performance byreducing the junction temperatures by 14 K and 16 K on average,respectively. While RSHP and DSHP possess an excellent ability toremoving the generated heat, microchannels have also been implemented inthe electronic cooling systems to improve the thermal performance [10].

Microchannel heat sinks which were first proposed by Tuckerman and Pease[11], have been investigated and tested as high performance and compactcooling schemes. Both the industry and research communities haveinvestigated the use of high performance microchannels on 3D ICstructures. The works from IBM (Armonk, NY) [12-13] illustrate thestructure and fabrication process of the integrated single-layermicrochannel (SLMC) for 3D ICs. The SLMCs are distributed among devicelayers. Cooling fluid is delivered to the 3D ICs by employing fluidicthrough silicon vias (TSVs) and fluidic pipes [13].

With this configuration, Mizunuma et al. [14] developed a fast andaccurate thermal-wake model for integrated SLMC 3D IC structure whichshows that the integrated SLMC 3D IC reduces the junction temperaturesignificantly. Lu et al. [15] investigated a Multiphysics-basedco-simulation technique for the performance of 3D IC structure withintegrated SLMC cooling. The integrated SLMC effectively reduced thehotspot temperature and achieved a more uniform temperaturedistribution. Feng et al. [16] focused on the fast and accurateGPU-based solver development and they showed that integrated SLMCcooling is effective in improving the thermal performance of 3D ICs.

One drawback of SLMC heat sink is the relatively higher streamwisetemperature rise. This undesirable temperature gradient produces thermalstresses in IC packages and undermines both the thermal performance andthe electrical performance [1-3]. Double-layer or multi-layermicrochannels (DLMC or MLMC) can contribute to resolve these problems.DLMC and MLMC were first introduce by Vafai and Zhu [17-19]. DLMC andMLMC are not only excellent in reducing the undesired temperaturevariation in the streamwise direction thus enhancing the overall coolingcapacity compared to the SLMC, but also have lower pressure drop andrequire less pumping power [17-20].

It should be noted that the counter-flow layout was implemented in Vafaiand Zhu's works [17-19]. Following Vafai and Zhu [17-19], Xie et al.[21-24] explored straight and wavy rectangular DLMC with parallel-flowand counter-flow layouts. Their results show that the counter-flow DLMChas superior thermal performance, more uniform temperature rise andlower overall thermal resistance for various scenarios. The otherlimitation of the integrated SLMC on 3D ICs studied in [12-16] is thesignificant increased risk of water permanently damaging the 3D ICstructure due to the fact that the integrated SLMCs among the devicelayers requires the fluidic TSVs and pipes to deliver the water into thestructure.

To resolve the above problems, this work introduces the integratedchip-size DLMC and MLMC on top and bottom of the 3D IC structures toavoid the fluidic TSVs and pipes within the dies and improve the overallcooling performance. The hotspot temperature reductions and thesubstantial weight and size reduction of the heat sink equipment indiverse configurations of integrated DLMC and MLMC are thoroughlyillustrated. In addition, optimization of the integrated DLMC and MLMCis discussed, including adding a heat sink on top of the structure, thechange of the dimensions of the DLMC and investigation of nanofluidswithin the DLMC.

BRIEF SUMMARY

The following summary is provided to facilitate an understanding of someof the innovative features unique to the disclosed embodiments and isnot intended to be a full description. A full appreciation of thevarious aspects of the embodiments disclosed herein can be gained bytaking the entire specification, claims, drawings, and abstract as awhole.

It is, therefore, one aspect of the disclosed embodiments to provide foran improved integrated circuit.

It is another aspect of the disclosed embodiments to provide for animproved 3D integrated circuit.

The aforementioned aspects and other objectives and advantages can nowbe achieved as described herein.

In an embodiment, a three-dimensional integrated circuit apparatus, caninclude a three-dimensional integrated circuit comprising a substrateand a plurality of integrated double-layer microchannels (DLMC) andmulti-layer microchannels (MLMC) with optimized thermal performance forthe three-dimensional integrated circuit, wherein the plurality ofintegrated double-layer microchannels (DLMC) and multi-layermicrochannels (MLMC) are located above the substrate.

In an embodiment, the three-dimensional integrated circuit can comprisea metal-oxide semiconductor-integrated circuit.

In an embodiment, a heat source can be uniformly distributed in eachlayer of a plurality of layers of the three-dimensional integratedcircuit and can be conducted through the plurality of layers down to thesubstrate and up to a spreader and a heat sink, and eventually toambient air through forced convective heat transfer above the heat sinkand natural convective heat transfer under the substrate.

In an embodiment, a three-dimensional integrated circuit apparatus, caninclude a three-dimensional integrated circuit including a group ofintegrated double-layer microchannels (DLMC) and multi-layermicrochannels (MLMC) with optimized thermal performance for thethree-dimensional integrated circuit.

In an embodiment, chip-size integrated double-layer microchannels (DLMC)and multi-layer microchannels (MLMC) can be used to optimize the thermalperformance of three-dimensional integrated circuits (3D ICs). Thechip-size integrated DLMC without a heat spreader and a heat sink canreduce the hotspot temperature for a nominal 3D IC structure.

In an embodiment, the size is significantly smaller than copper heatsinks and the weight of the chip-size integrated DLMC can be reduced by99.9%.

Furthermore, in an embodiment, two chip-size integrated DLMCs can lowerthe hotspot temperature compared with utilizing just one integrated DLMCon top of the chip structure. Results show that the disclosedmulti-layer microchannels (MLMC) have a great effect on reducing thehotspot temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures, in which like reference numerals refer toidentical or functionally-similar elements throughout the separate viewsand which are incorporated in and form a part of the specification,further illustrate the present invention and, together with the detaileddescription of the invention, serve to explain the principles of thepresent invention.

FIG. 1 illustrates a schematic diagram of the structure of athree-dimensional integrated circuit, in accordance with an embodiment;

FIG. 2 illustrates a schematic diagram of a three-dimensional integratedcircuit including a heat pipe comprising a heat sink or a heat spreader,in accordance with an embodiment;

FIG. 3A illustrates a schematic diagram of a chip-size integrateddouble-layer microchannels (DLMC) structure, in accordance with anembodiment;

FIG. 3B illustrates a magnified view of a set of channels of thechip-size integrated DLMC structure shown in FIG. 3A, in accordance withan embodiment;

FIG. 4 illustrates a schematic diagram of a chip-size integrated DLMC ontop of a 3D IC structure, in accordance with an embodiment;

FIG. 5 illustrates a schematic diagram of a chip-size integrated DLMC ontop of a 3D IC structure with a heat sink thereabove, in accordance withan embodiment;

FIG. 6 illustrates a schematic diagram of a two chip-size integratedDLMC on top and at the bottom of a 3D IC structure, in accordance withan embodiment;

FIG. 7 illustrates a schematic diagram of a two chip-size integratedDLMC on top and at the bottom of a 3D IC structure with a heat sinkthereabove, in accordance with an embodiment;

FIG. 8 illustrates a schematic diagram of a chip-size integratedthree-layer microchannel on top of a 3D IC structure, in accordance withan embodiment;

FIG. 9 illustrates a schematic diagram of a chip-size integrated MLMC ontop of a 3D IC structure, in accordance with an embodiment;

FIG. 10 illustrates a graph depicting data indicative of a gridindependence study for the investigated structures discussed herein, inaccordance with an embodiment;

FIG. 11 illustrates a graph depicting the temperature distribution ofthe bottom surface of a DLMC with both counter-flow and parallel-flowlayout, in accordance with an embodiment; and

FIG. 12 illustrates a graph depicting data indicative of the effects ofnanofluids within the integrated DLMC on the hotspot temperature, inaccordance with an embodiment.

DETAILED DESCRIPTION

The particular values and configurations discussed in these non-limitingexamples can be varied and are cited merely to illustrate one or moreembodiments and are not intended to limit the scope thereof.

Subject matter will now be described more fully hereinafter withreference to the accompanying drawings, which form a part hereof, andwhich show, by way of illustration, specific example embodiments.Subject matter may, however, be embodied in a variety of different formsand, therefore, covered or claimed subject matter is intended to beconstrued as not being limited to any example embodiments set forthherein; example embodiments are provided merely to be illustrative.Likewise, a reasonably broad scope for claimed or covered subject matteris intended. Among other things, for example, subject matter may beembodied as methods, devices, components, or systems. Accordingly,embodiments may, for example, take the form of hardware, software,firmware, or any combination thereof (other than software per se). Thefollowing detailed description is, therefore, not intended to beinterpreted in a limiting sense.

Throughout the specification and claims, terms may have nuanced meaningssuggested or implied in context beyond an explicitly stated meaning.Likewise, phrases such as “in one embodiment” or “in an exampleembodiment” and variations thereof as utilized herein do not necessarilyrefer to the same embodiment and the phrase “in another embodiment” or“in another example embodiment” and variations thereof as utilizedherein may or may not necessarily refer to a different embodiment. It isintended, for example, that claimed subject matter include combinationsof example embodiments in whole or in part. In addition, identicalreference numerals utilized herein with respect to the drawings canrefer to identical or similar parts or components.

In general, terminology may be understood, at least in part, from usagein context. For example, terms such as “and,” “or,” or “and/or” as usedherein may include a variety of meanings that may depend, at least inpart, upon the context in which such terms are used. Typically, “or” ifused to associate a list, such as A, B, or C, is intended to mean A, B,and C, here used in the inclusive sense, as well as A, B, or C, hereused in the exclusive sense. In addition, the term “one or more” as usedherein, depending at least in part upon context, may be used to describeany feature, structure, or characteristic in a singular sense or may beused to describe combinations of features, structures, orcharacteristics in a plural sense. Similarly, terms such as “a,” “an,”or “the”, again, may be understood to convey a singular usage or toconvey a plural usage, depending at least in part upon context. Inaddition, the term “based on” may be understood as not necessarilyintended to convey an exclusive set of factors and may, instead, allowfor existence of additional factors not necessarily expressly described,again, depending at least in part on context.

Embodiments relate to a chip-size integrated double-layer microchannels(DLMC) and multi-layer microchannels (MLMC) that can optimize thethermal performance of three-dimensional integrated circuits (3D ICs).In an example embodiment, the chip-size integrated DLMC without a heatspreader and a heat sink reduced the hotspot temperature by almost 15 Kfor a nominal 3D IC structure. Meanwhile, the size is significantlysmaller than the copper heat sinks and the weight of the chip-sizeintegrated DLMC was reduced by 99.9%. Furthermore, two chip-sizeintegrated DLMCs can lower the hotspot temperature by another 6.77 Kcompared with utilizing just one integrated DLMC on top of the chipstructure. The results also show that the multi-layer microchannels(MLMC) have a great effect on reducing the hotspot temperature. We haveestablished that the optimal layout is 4 layers. The hotspot temperaturecan be reduced by 21 K and 102 times lighter in weight compared tonominal 3D IC structure. The proposed structure and results presentedherein can pave the way for major innovations in resolving the thermalissues for the 3D ICs.

FIG. 1 illustrates a schematic diagram of the structure of athree-dimensional integrated circuit 10, in accordance with anembodiment. The three-dimensional integrated circuit 10 can include asubstrate 36 upon which a variety of layers and components may beconfigured. A layer 34 comprising a TIM layer with C4 bump can beconfigured above the substrate 36. A first die layer 32 can beconfigured on and above the layer 34. A device layer 30 can be formedabove the first die layer 32. A layer 28 comprising a TIM layer withmicrobump(s) can be configured above the layer 30.

A second die layer 26 can be formed above the layer 28. A device layer24 can be formed above the second die layer 26. A layer 22 comprising aTIM layer with microbump(s) can be formed above the device layer 24. Athird die layer 20 can be configured above the layer 22. A device layer18 can be formed above layer 20. A layer 16 comprising a TIM layer withmicrobump(s) can be formed above the layer 18. A heat spreader 14 can beformed above the layer 16. A heat sink 12 can be formed above the heatspreader 14.

Note that the term “TIM layer with microbump(s)” as utilized herein inthe context of an integrated circuit (IC) formed on a substrate, canrelate to a Thermal Interface Material (TIM) layer that can be utilizedto improve heat dissipation and thermal conductivity between the IC andits surrounding components or heatsink.

When the IC operates, it generates heat, which needs to be efficientlydissipated to prevent overheating and maintain optimal performance. TheTIM layer can act as a thermal bridge, facilitating the transfer of heatfrom the IC to the surrounding components or a heatsink.

Microbumps, on the other hand, are small solder or metal bumps locatedon the surface of the IC or substrate. They can be used to establishelectrical connections between different layers or components within theIC, such as connecting the IC to a package substrate.

By combining a TIM layer with microbumps, the thermal conductivity andelectrical connectivity can be simultaneously enhanced. The microbumpsprovide electrical connections while also creating additional contactpoints for heat transfer between the IC and the heatsink or othercooling mechanisms. The TIM layer can fill the gaps between the IC andthe heatsink, thereby reducing thermal resistance and improving overallheat dissipation. This combination of a TIM layer with microbumps canhelp to address both thermal management and electrical connectivityrequirements in integrated circuits, ensuring efficient heat dissipationwhile maintaining reliable electrical performance.

FIG. 2 illustrates a schematic diagram of a three-dimensional integratedcircuit 11 including a heat pipe 15 as a heat sink or a heat spreader,in accordance with an embodiment. The three-dimensional integratedcircuit 11 shown in FIG. 1 is similar to the three-dimensionalintegrated circuit 10 depicted in FIG. 1 , but with some differencesincluding the heat pipe 15 functioning a heat sink or a heat spreader,and a layer 13 comprising a flat-shaped heat pipe.

Schematics of nominal 3D IC structures are shown in FIG. 1 and FIG. 2 .The nominal 3D IC structure includes a substrate, thermal interfacematerial (TIM) with C4 bumps, three layers of dies, device layers andTIM with microbumps, a heat spreader and a heat sink on top. Four coreprocessors, fabricated on each device layer, are the main heat sources.

Table 1 displays the nominal values for different components of the 3DIC structure for nominal cases. The chip-size DLMC structure fabricatedwith copper [10, 15, 25-31], as illustrated in FIG. 3A and FIG. 3B, is10×10 mm² and the dimensions for channel width, channel height, finwidth, and base and cover thickness are presented in Table 2.

TABLE 2 Nominal Values within the DLMC strcuture Channel base/coverNumber of Channel Length Channel Width Channel Height Channel fin widththickness Channels L (mm) W_(c) (μm) H_(c) (μm) W_(f) (μm) H_(t) (μm) NStructure 10 290 400 200 50 20 × 2 References [13, 15, 16, 21, 24-28]

The heat source is uniformly distributed [9] in each layer (e.g., 30 Weach layer and 7.5 W each processor). The heat can be conducted throughthe layers down to the substrate and up to the spreader and the heatsink, and eventually to the ambient air through forced convective heattransfer above the heat sink and natural convective heat transfer underthe substrate. Conductive heat transfer through the solid, and isotropiclayers of the 3D IC can be governed by

$\begin{matrix}{{\frac{\partial^{2}\Theta_{s}^{+}}{\partial x^{+ 2}} + \frac{\partial^{2}\Theta_{s}^{+}}{\partial y^{+ 2}} + \frac{\partial^{2}\Theta_{s}^{+}}{\partial z^{+ 2}} + q_{g}^{+}} = 0} & (1)\end{matrix}$

Where q_(g) ⁺ denotes the dimensionless volumetric heat generation inthe central processing units and the nondimensionalized temperature andspatial coordinates are set up as:

${x^{+} = \frac{x}{h}},{y^{+} = \frac{y}{h}},{z^{+} = \frac{z}{h}},{\Theta^{+} = \frac{T - T_{e}}{{qh}/k_{f}}}$

The convective boundary conditions are

$\begin{matrix}{\frac{\partial\Theta_{s}^{+}}{\partial n^{*}} = {{- {Bi}} \cdot \Theta_{s}^{+}}} & (2)\end{matrix}$

When the IC operates, it generates heat, which needs to be efficientlydissipated to prevent overheating and maintain optimal performance. TheTIM layer can act as a thermal bridge, facilitating the transfer of heatfrom the IC to the surrounding components or a heatsink. Where n* is thenormal coordinate and Bi is the dimensionless Biot number. Nominally,the heat flow occurs mainly normal to the device layers. The heattransfer and fluid flow for the DLMC needs to be accounted for. It isgoverned by the Navier-Stokes equation. The water as the coolant withinthe microchannel is pumped into the channel at 1 m/s [13]. Thedimensionless Navier-Stokes equations in Cartesian coordinates are:

Mass Conservation:

$\begin{matrix}{{\frac{\partial u^{+}}{\partial x^{+}} + \frac{\partial v^{+}}{\partial y^{+}} + \frac{\partial w^{+}}{\partial z^{+}}} = 0} & (3)\end{matrix}$

x-Momentum Equation:

$\begin{matrix}{{{Re}_{h}\left( {{u^{+}\frac{\partial u^{+}}{\partial x^{+}}} + {v^{+}\frac{\partial u^{+}}{\partial y^{+}}} + {w^{+}\frac{\partial u^{+}}{\partial z^{+}}}} \right)} = {{- \frac{\partial p^{+}}{\partial x^{+}}} + \left( {\frac{\partial^{2}u^{+}}{\partial x^{+ 2}} + \frac{\partial^{2}u^{+}}{\partial y^{+ 2}} + \frac{\partial^{2}u^{+}}{\partial z^{+ 2}}} \right)}} & (4)\end{matrix}$

y-Momentum Equation:

$\begin{matrix}{{{Re}_{h}\left( {{u^{+}\frac{\partial v^{+}}{\partial x^{+}}} + {v^{+}\frac{\partial v^{+}}{\partial y^{+}}} + {w^{+}\frac{\partial v^{+}}{\partial z^{+}}}} \right)} = {{- \frac{\partial p^{+}}{\partial y^{+}}} + \left( {\frac{\partial^{2}v^{+}}{\partial x^{+ 2}} + \frac{\partial^{2}v^{+}}{\partial y^{+ 2}} + \frac{\partial^{2}v^{+}}{\partial z^{+ 2}}} \right)}} & (5)\end{matrix}$

z-Momentum Equation:

$\begin{matrix}{{{Re}_{h}\left( {{u^{+}\frac{\partial w^{+}}{\partial x^{+}}} + {v^{+}\frac{\partial w^{+}}{\partial y^{+}}} + {w^{+}\frac{\partial w^{+}}{\partial z^{+}}}} \right)} = {{- \frac{\partial p^{+}}{\partial z^{+}}} + \left( {\frac{\partial^{2}w^{+}}{\partial x^{+ 2}} + \frac{\partial^{2}w^{+}}{\partial y^{+ 2}} + \frac{\partial^{2}w^{+}}{\partial z^{+ 2}}} \right)}} & (6)\end{matrix}$

Energy Conservation for the Fluid Domain:

$\begin{matrix}{{{Pe}_{h}\left( {{u^{+}\frac{\partial\Theta_{f}^{+}}{\partial x^{+}}} + {v^{+}\frac{\partial\Theta_{f}^{+}}{\partial y^{+}}} + {w^{+}\frac{\partial\Theta_{f}^{+}}{\partial z^{+}}}} \right)} = {\frac{\partial^{2}\Theta_{f}^{+}}{\partial x^{+ 2}} + \frac{\partial^{2}\Theta_{f}^{+}}{\partial y^{+ 2}} + \frac{\partial^{2}\Theta_{f}^{+}}{\partial z^{+ 2}}}} & (7)\end{matrix}$

The Nondimensionalized Terms in the Above Equations are:

${u^{+} = \frac{u}{u_{m}}},{v^{+} = \frac{v}{v_{m}}},{w^{+} = \frac{w}{w_{m}}},{p^{+} = \frac{ph}{\mu_{f}u_{m}}},{{Re}_{h} = \frac{\rho_{f}u_{m}h}{\mu_{f}}},\ {{Pe_{h}} = \frac{\rho_{f}c_{p,f}u_{m}h}{k_{f}}}$

This work also investigates Al₂O₃ nanofluids within the DLMC to furtheroptimize the thermal performance with higher thermal conductivity. Thethermal conductivity, dynamic viscosity, density and specific heat ofAl₂O₃ nanofluids are calculated as follows [32-35]:

$\begin{matrix}{k_{nf} = {\left\lbrack \frac{k_{p} + {\left( {n - 1} \right)k_{bf}} - {\left( {n - 1} \right){\varphi\left( {k_{bf} - k_{P}} \right)}}}{k_{p} + {\left( {n - 1} \right)k_{bf}} + {\varphi\left( {k_{bf} - k_{P}} \right)}} \right\rbrack k_{bf}}} & (8)\end{matrix}$ $\begin{matrix}{\mu_{nf} = {\left( {1 + {2.5\varphi}} \right)\mu_{bf}}} & (9)\end{matrix}$ $\begin{matrix}{\rho_{nf} = {{\left( {1 - \varphi} \right)\rho_{bf}} + {\varphi\rho}_{P}}} & (10)\end{matrix}$ $\begin{matrix}{c_{p,{nf}} = {{\left( {1 - \varphi} \right)c_{p,{bf}}} + {\varphi c_{p,P}}}} & (11)\end{matrix}$

Where k_(nf), k_(bf) and k_(p) are the thermal conductivities of Al₂O₃the nanofluid, base fluid and solid particles, respectively. φ is thevolumetric concentration of nanoparticles and n is solid particle shapefactor (n=3 with the assumption of spherical particles). μ_(nf) andμ_(bf) are the viscosities of the nanofluid and base fluid,respectively; ρ_(nf), ρ_(bf) and ρ_(P) are the densities of nanofluid,base fluid and solid particles, respectively; c_(p,nf), c_(p,bf) andc_(p,P) are the specific heat of the nanofluid, base fluid and solidparticles, respectively. The calculated results for the above-mentionedproperties are listed in Table 3.

TABLE 3 Al₂O₃ nanofluid properties φ = 0% φ = 2% φ = 5% k_(nf) (w/m · K)0.603 0.638 0.693 ρ_(nf) (kg/m³) 995.7 1047.7 1125.9 μ_(nf) (kg/m · s)7.977 × 10⁻⁴ 8.376 × 10⁻⁴ 8.974 × 10⁻⁴ c_(p, nf) (kJ/kg · K) 4.183 4.1154.012

TABLE 1 Nominal values for various parameters within the 3D IC structure[9] Layer Parameter Nominal Value Unit Heat sink Material Cu Length &Width 50 mm Thickness 4/29.4 mm Rectangular- Material Cu shaped heatLength & Width 50 mm pipe Thickness 29.4 mm Disk- Material Cu shapedheat Radius 28 mm pipe Thickness 29.4 mm Heat spreader Material CuLength & Width 30 mm Thickness 3 mm Chip Length & Width 10 mm Number oflayers 3 mm TIM layer with TIM material Thermal grease microbump Thermalconductivity 5 W/m · K Thickness 15 μm TIM layer with TIM materialThermal grease C4 bump Thermal conductivity 5 W/m · K Thickness 100 μmDie Material Si Thickness 100 μm Device layer Material Si Thickness 2 μmCore processor Material Si Total power within 90 W the 3D IC Cores perlayer 4 Length & Width 2 mm Thickness 2 μm Substrate Material Si Length& Width 30 mm Thickness 1 mm

FIG. 3A illustrates a schematic diagram of a chip-size integrated DLMCstructure 40, in accordance with an embodiment. The chip-size integratedDLMC structure 40 can be configured with a set of channels, examples ofwhich are channels 42 including channels 43 and 45. FIG. 3B illustratesa magnified view of the set of channels 42 of the chip-size integratedDLMC structure 40 shown in FIG. 3A, in accordance with an embodiment.

FIG. 4 illustrates a schematic diagram of a 3D IC 54 with the chip-sizeintegrated DLMC 40 on top of a 3D IC structure, in accordance with anembodiment. Note that the 3D IC structure may include a plurality oflayers 56 formed on the substrate 36. Examples of such a 3D IC structureinclude the three-dimensional integrated circuit 10 andthree-dimensional integrated circuit 11 shown respectively in FIG. 1 andFIG. 2 . In the interest of brevity not every layer and component isdescribed with respect to FIG. 4 through FIG. 9 .

FIG. 5 illustrates a schematic diagram of a 3D IC 60 including achip-size integrated DLMC 60 on top of a 3D IC structure with a heatsink 58 thereabove, in accordance with an embodiment.

FIG. 6 illustrates a schematic diagram of a 3D IC 62 with a twochip-size integrated DLMC 40 and 41 respectively on top and at thebottom of a 3D IC structure, in accordance with an embodiment.

FIG. 7 illustrates a schematic diagram of a 3D IC 64 having a twochip-size integrated DLMC on top and at the bottom of a 3D IC structurewith a heat sink 48 thereabove, in accordance with an embodiment.

FIG. 8 illustrates a schematic diagram of a 3D IC 66 including achip-size integrated three-layer microchannel structure 45 on top of a3D IC structure, in accordance with an embodiment.

FIG. 9 illustrates a schematic diagram of a 3D IC 68 with a chip-sizeintegrated MLMC 47 on top of a 3D IC structure, in accordance with anembodiment.

The simulation and modeling of the thermal performance can be carriedout through COMSOL Multiphysics. A grid independence study was performedfor all investigated structures (e.g., FIG. 4 -FIG. 9 ) and the junctiontemperature for each structure was evaluated using computational meshesfor different cell distributions. The grid independence study forvarious cases applying physics-based coarse, fine, finer, normal andextra fine mesh distributions is shown in FIG. 10 .

FIG. 10 illustrates a graph 100 depicting data indicative of a gridindependence study for the investigated structures discussed herein, inaccordance with an embodiment. The overall temperature varies within 1K. In order to reduce the computational time and gain accuratesimulation results, the normal mesh distribution is sufficient to obtainaccurate results and is employed in this work.

Note that the aforementioned COMSOL Multiphysics is a software packagedesigned for simulation and modeling of physical phenomena acrossmultiple disciplines. It provides engineers, researchers, and scientistswith a comprehensive environment for analyzing and solving complexmultiphysics problems.

COMSOL Multiphysics employs the finite element method (FEM) as theunderlying numerical technique for solving partial differentialequations (PDEs). It allows users to define their physical models andsimulate the behavior of various systems by specifying the governingequations, boundary conditions, and material properties.

In addition, the main feature of the 3D IC structure model discussedherein can be validated earlier [9] both experimentally and numerically.The DLMC model was compared with the work of Xie et al. [21] in FIG. 11. FIG. 11 illustrates an excellent agreement for the temperaturedistribution for a DLMC for both parallel-flow and counterflow structurebetween the present work and reference [21]. FIG. 11 illustrates a graph110 depicting the temperature distribution of the bottom surface of aDLMC with both counter-flow and parallel-flow layout, in accordance withan embodiment;

FIG. 12 illustrates a graph 120 depicting data indicative of the effectsof nanofluids within the integrated DLMC on the hotspot temperature, inaccordance with an embodiment.

Table 4 displays the thermal performance and weight comparison amongnominal copper heat sink (FIG. 1 ), RSHP and DSHP (FIG. 2 ) andintegrated chip-size DLMC (FIG. 4 ). It should be noted that the heightfor the nominal copper heat sink in this scenario is 29.4 mm in order tobe consistent with the height of RSHP and DSHP. Compared with thenominal 3D IC structure with copper heat sink and heat spreader (FIG. 1), RSHP as the heat sink reduced the hotspot temperature by 6K and DSHPreduced the hotspot temperature by 16K while reducing the weight by 7.35times. As it can be seen from Table 4, the chip-size integrated DLMCwithout a heat spreader and a heat sink, as illustrated in FIG. 4 ,reduced the hotspot temperature by almost 15 K. Meanwhile, the weight ofthe chip-size integrated DLMC is 1288 times lighter and the size issignificantly smaller than the copper heat sink.

TABLE 4 Comparison of the Thermal Performance among different heat sinksIntegrated DLMC without Copper RSHP DSHP a heat heat as the as thespreader sink/ heat heat and heat Reference sink sink sink (FIG. 1)(FIG. 2) (FIG. 2) (FIG. 4) Hotspot 339.2 333.7 323.3 324.5 Temperature(K) Reduction Reference 5.5 15.9 14.7 on Hotspot Temperature (K) WeightReduction Reference 7.35 times 7.35 times 1288 times lighter lighterlighter

As shown in Table 5, the heat sink with a nominal height of 4 mm on topof the chip-size integrated DLMC (FIG. 5 ) can further optimize thethermal performance of the 3D IC structure. Next, we have employed theeffect of combining a heat sink (copper heat sink, RSHP and DSHP asillustrated in FIGS. 1 and 2 ) and a chip-size integrated DLMC on thehotspot temperature. Integrated DLMC with a copper heat sink, RSHP andDSHP reduced the hotpot temperature by 18 K, 14 K and 3 K respectivelycompared with the combination of a heat sink and a heat spreader. Itshould be noted that the weight of the integrated DLMC is 51 timeslighter in weight and 9 times smaller in volume than the heat spreaderemployed in FIGS. 1 and 2 .

TABLE 5 The Combination of heat sinks with Integrated DLMC Copper heatIntegrated Integrated Integrated sink DLMC DLMC DLMC with with a with awith a copper copper RSHP DSHP heat heat heat heat spreader sink sinksink (FIG. 1) (FIG. 5) (FIG. 5) (FIG. 5) Hotspot 339.2 321 320 320Temperature (K) Reduction Reference 18.2 19.2 19.2 on HotspotTemperature (K) Weight Reduction Integrated DLMC is 51 times lighterthan the copper heat spreader and 9 times smaller in volume

Finally, we analyzed the effect of two chip-size integrated DLMC on topand at the bottom of the 3D IC structure, as displayed in FIGS. 6 and 7, on the hotspot temperature. The results shown in FIG. 12 clarify thesubstantial effect of this structure. Two chip-size integrated DLMClowered the hotspot temperature by another 6.77 K in comparison withemploying just one integrated DLMC for 3D IC regardless of having a heatsink on top or not. But having a heat sink on top can definitely improvethe thermal performance even further and the set-up can still remainlighter weight compared with the nominal structures (FIGS. 1 and 2 ).

FIG. 12 The effect of two integrated DLMC on the hotspot temperature ofthe 3D IC. The effect of multi-layer microchannels on the hotspottemperature of the 3D IC structure (FIGS. 8 and 9 ) is illustrated inTable 6. As it can be seen the optimal layout is 4 layers. The hotspottemperature is reduced by 21 K and the setup is 102 times lighter inweight compared to the nominal 3D IC structure with a nominal height of7 mm (FIG. 1 ). Meanwhile, the total height of the integrated 4-layermicrochannel is only 1.9 mm while the nominal 3D IC (FIG. 1 ) is 7 mm.After 4 layers, the decrease in the hotspot temperature is notsignificant while the weight and size increase significantly.

TABLE 6 Multilayer Micorchannel Hotspot temperaure Hotspot Total WeightTemperature (K) height (mm) Reduction Coper heat sink 339.2 7 Referencewith a heat spreader (FIG. 1) 2 layers 324.5 1 228 times (FIG. 4)lighter 3 layers 320.28 1.45 133 times (FIG. 8) lighter 4 layers 317.851.9 102 times (FIG. 9) lighter 5 layers 316.91 2.35 84 times (FIG. 9)lighter 6 layers 316.27 2.8 71 times (FIG. 9) lighter

To further optimize the thermal performance of the 3D IC structure, morenarrower channels were utilized with the same chip-size integrated DLMC.FIG. 13 shows that when the number of channels increased from N=40 toN=50, the hotspot temperature is lowered by 2 K. The effect is notsignificant. The effect of nanofluids (Al₂O₃) within the integrated DLMCon the hotspot temperature of the 3D ICs was also explored. Three caseswere selected to show the impact of the nanofluids. Case 1 is theintegrated DLMC with 40 channels and cases 2 is for 50 channels. Case 3was based on the two integrated DLMC with a copper heat sink above whileincreasing the volume fraction of the nanofluids. FIG. 13 shows that theinfluence of nanofluids also is insignificant. The hotspot temperaturewas reduced by 1 K when the volume fraction was increased from 2% to 5%for all three cases.

A thorough analysis and optimization of the thermal performance of the3D ICs utilizing the chip-size integrated DLMC and MLMC is presented inthis work. The results demonstrate that the integrated DLMC and MLMC notonly substantially contribute to improve the thermal performance of the3D ICs and reduce the hotspot temperature but also greatly reduce theoverall packaging size and weight, which is in high demand for theelectronic devices in the industry. The main contributions for anintegrated DLMC and MLMC are as follows:

(1). The chip-size integrated DLMC without a heat spreader and a heatsink reduce the hotspot temperature by almost 15 K compared with thenominal structure. Meanwhile, the weight of the chip-size integratedDLMC is 1288 times lighter and the size is significantly smaller thanthe combination of copper heat sinks and heat spreaders.

(2). Two chip-size integrated DLMC on top and bottom of the chip loweredthe hotspot temperature by another 6.77 K in comparison of only oneintegrated DLMC on top of the IC structure. The total temperaturereduction in this case was 21 K and the weight was reduced by 99%.

(3). The MLMC has a pronounced effect on reducing the hotspottemperature. The optimal layout was demonstrated to be 4 layers. Thehotspot temperature was reduced by 21 K and the structure was 102 timeslighter in weight compared to the nominal 3D IC structure.

(4). Integrating a heat sink on top of the DLMC or MLMC without a heatspreader further reduced the hotspot temperature by another 4 K for atotal hot spot temperature reduction up to 25 K. Compared to the heatspreader in the nominal structure, a chip-size DLMC is 51 times lighterin weight and 9 times smaller in volume.

(5) The effect of utilizing nanofluids for the 3D IC structure was alsoinvestigated and the results were presented. It was shown that thenanofluids did not create a significant reduction within the analyzedproposed innovative 3D IC structure.

It will be appreciated that variations of the above-disclosed and otherfeatures and functions, or alternatives thereof, may be desirablycombined into many other different systems or applications. It will alsobe appreciated that various presently unforeseen or unanticipatedalternatives, modifications, variations or improvements therein may besubsequently made by those skilled in the art which are also intended tobe encompassed by the following claims.

NOMENCLATURE L Channel length [mm] W_(c) Channel width [μm] H_(c)Channel height [μm] W_(f) Channel fin width [μm] h_(t) Channel cover andbase thickness [μm] N Number of channels k Thermal conductivity [W (m ·K)⁻¹] n* Normal coordinate Bi Biot number p Pressure [Pa] u x-componentof velocity [m · s⁻¹] v y-component of velocity [m · s⁻¹] w z-componentof velocity [m · s⁻¹] x, y, z Cartesian coordinates Re_(h) Reynoldsnumber c_(p) Specific heat at constant pressure [J (kg · K)⁻¹] Pe_(h)Peclet number q Heat flux [W · m⁻²] q_(g) Volumetric heat generationrate [W · m⁻³] T Temperature [K] n Solid particle shape factor Greeksymbols φ Volumetric concentration of nanoparticles Θ Dimensionlesstemperature ρ Density [kg · m⁻³] μ Dynamic viscosity [(N · s)m⁻²]Subscripts f Fluid s Solid m Mean nf nanofluid bf Base fluid Pnanoparticle Superscripts + Dimensionless quantities

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1. A three-dimensional integrated circuit apparatus, comprising: athree-dimensional integrated circuit comprising a substrate and aplurality of integrated double-layer microchannels (DLMC) andmulti-layer microchannels (MLMC) with optimized thermal performance forthe three-dimensional integrated circuit, wherein the plurality ofintegrated double-layer microchannels (DLMC) and multi-layermicrochannels (MLMC) are located above the substrate.
 2. Thethree-dimensional integrated circuit apparatus of claim 1 wherein thethree-dimensional integrated circuit comprises a metal-oxidesemiconductor-integrated circuit.
 3. The three-dimensional integratedcircuit apparatus of claim 1 wherein a heat source is uniformlydistributed in each layer of a plurality of layers of thethree-dimensional integrated circuit and is conducted through theplurality of layers down to the substrate and up to a spreader and aheat sink, and eventually to ambient air through forced convective heattransfer above the heat sink and natural convective heat transfer underthe substrate.
 4. A three-dimensional integrated circuit apparatus,comprising: a three-dimensional integrated circuit including a group ofintegrated double-layer microchannels (DLMC) and multi-layermicrochannels (MLMC) with optimized thermal performance for thethree-dimensional integrated circuit.